Power Optimization of Delay Constrained Circuits

We present a framework for combining Voltage Scaling and Gate sizing techniques for power optimizations. Our results show that the combination of the two techniques perform better than the techniques applied in isolation. We introduce a new heuristic for choosing gates for sizing and voltage scaling such that the total power is minimized under delay constraints. We also use a more accurate estimate for determining the power dissipation of the circuit by taking into account the short circuit power along with the dynamic power. A better model of the short circuit power is used which takes into account the loading capacitance of the gates. Our results show an average power reduction of 73 % when decisions are taken assuming dynamic power only and an average power reduction of 77 % when decisons include the short circuit power dissipation. The circuit under consideration are delay contrained and rst optimized for delay under the environment of SIS.